Analysis of Leakage Power Reduction in 6T SRAM Cell

On chip cache memories contributes a large fraction to the total power consumption of microprocessor. As technology scales down into d e e p -submicron, leakage power is becoming a dominant source of power consumption. As cache memory is an array structure leakage reduction in just one memory cell can on the whole reduce a large amount of leakage power. In this thesis leakage power of conventional 6T cell at 180nm technology has been evaluated and circuit level leakage reduction techniques such as Sizing of the transistor and Gated VDD has been discussed and applied on conventional 6T cache memory cell. By the sizing of the transistors in SRAM cell an optimized 6T SRAM cell is obtained and evaluated and found to be more efficient than the conventional SRAM Cell. After that Gated-VDD is applied on the optimized 6T SRAM Cell and it is found to be most efficient in terms of leakage power. Keyword: SRAM 6T Cell, Leakage Power Reduction, Sizing of transistor, Gated-VDD, Cadence tool